An energy-efficient 5-MHz to 20-MHz, 12-bit reconfigurable continuous-time ΣΔ modulator for 4G-LTE application

• Published in: International Symposium on Low Power Electronics and Design (ISLPED) pp. 163 - 168
• Main Authors: Jing Li, Ruiyuan Zhu, Ting Yi, Bill Liu, Zhiliang Hong
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.09.2013
• Subjects: Bandwidth; Clocks; CT ΣΔ modulator; Energy efficiency; energy efficiency optimization; interpolating multi-bit quantizer; Jitter; Modulation; multi-band reconfigurable; Switches; Topology
• DOI: 10.1109/ISLPED.2013.6629288

This paper presents an energy-efficient reconfigurable 3 rd -order continuous-time ΣΔ modulator, which can satisfy multi-band modes for 4G-LTE application. To expand the reconfigurable bandwidth range and optimize the energy efficiency, this work employs a flexible architecture, which can switch between feed-forward and feed-back topologies. At the circuit level, in order to reduce power consumption, flexibility is also introduced into all the core blocks, including amplifiers, multi-bit quantizer and feedback DAC. In addition, multi-bit quantizer utilizes interpolating technique to relax the wide-band amplifier in terms of the low power design. A power-efficient three-stage amplifier with modified positive feedback compensation is used to process high-speed signal and enhance linearity of the modulator. Implemented in 130nm CMOS technology, this work achieves peak SNR of 72.7/66.7/60.4/59.0 dB over 5/10/15/20 MHz BW with 8/14.7/16/21 mW from 1.2V supply, and the respective FOMs are optimized to 227/443/657/773 fJ/conv.