Low-complexity high throughput VLSI architecture of soft-output ML MIMO detector

In this paper a VLSI architecture of a high throughput and high performance soft-output (SO) MIMO detector (the recently presented Layered ORthogonal Lattice Detector, LORD) is presented. The baseline implementation includes optimal (i.e. maximum-likelihood - ML - in the max-log sense) SO generation...

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Bibliographic Details
Published in2010 Design, Automation & Test in Europe Conference & Exhibition (DATE 2010) pp. 1396 - 1401
Main Authors Cupaiuolo, Teo, Siti, Massimiliano, Tomasoni, Alessandro
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2010
Subjects
Algorithm design and analysis
Detectors
Fading
Lattices
MIMO
OFDM
Receiving antennas
Throughput
Transmitting antennas
Very large scale integration
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Summary:In this paper a VLSI architecture of a high throughput and high performance soft-output (SO) MIMO detector (the recently presented Layered ORthogonal Lattice Detector, LORD) is presented. The baseline implementation includes optimal (i.e. maximum-likelihood - ML - in the max-log sense) SO generation. A reduced complexity variant of the SO generation stage is also described. To the best of the authors' knowledge, the proposed architecture is the first VLSI implementation of a max-log ML MIMO detector which includes QR decomposition and SO generation, having the latter a deterministic very high throughput thanks to a fully parallelizable structure, and parameterizability in terms of both the number of transmit and receive antennas, and the supported modulation orders. The two designs achieve a very high throughput making them particularly suitable for MIMO-OFDM systems like e.g. IEEE 802.11n WLANs: the most demanding requirements are satisfied at a reasonable cost of area and power consumption.
ISBN:1424470544
9781424470549
ISSN:1530-1591
1558-1101
DOI:10.1109/DATE.2010.5457031