A new event driven testbench synthesis engine for FPGA emulation

• Published in: 2011 9th IEEE International Conference on ASIC pp. 373 - 376
• Main Authors: Haocheng Huang, Aiwu Ruan, Yongbo Liao, Jianhua Zhu, Lin Wang, Chuanyin Xiang, Pin Li
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.10.2011
• Subjects: Engines; Field programmable gate arrays; Hardware design languages; Image edge detection; Parity check codes; Syntactics
• ISBN: 9781612841922; 1612841929
• ISSN: 2162-7541; 2162-755X
• DOI: 10.1109/ASICON.2011.6157199

FPGA emulation has long provided the highest performance. However, designers have to restrict their coding style or transforming a huge unsynthesizable testbench into synthesizable one by themselves due to usually unsynthesizable testbench. We address this problem by presenting a new event driven testbench synthesis engine called BeEmu (Behavior-Level Emulator) to translate the behavioral testbench into synthesizable one for FPGA emulation. The proposed testbench synthesis engine is built by hardware constructs in terms of event driven model to correspond with testbench. Experiments demonstrate that our proposed engine can not only have a high simulation speed, but cover more HDL syntax as well.