The Effects of Geometrical Capacitance Components of LOCOS Diode in VLSI

The effects of geometrical capacitance components of LOCal Oxidation of Silicon (LOCOS) diode in Very Large Scale Integrated circuit (VLSI) are proposed. For the correct circuit model simulation, the model of the device must be accurate and consistence with the SPICE models. The rectangular structur...

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Bibliographic Details
Published in2019 7th International Electrical Engineering Congress (iEECON) pp. 1 - 4
Main Authors Nissai, Itsariya, Ruangphanit, Anucha, Wongprasert, Yothin, Muanghlua, Rangson
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2019
Subjects
Capacitance
Integrated circuit modeling
junction capacitance
Junctions
LOCOS Diode
Semiconductor device measurement
Semiconductor device modeling
Substrates
Very large scale integration
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Summary:The effects of geometrical capacitance components of LOCal Oxidation of Silicon (LOCOS) diode in Very Large Scale Integrated circuit (VLSI) are proposed. For the correct circuit model simulation, the model of the device must be accurate and consistence with the SPICE models. The rectangular structure (L=400 μm, W=200 μm), the multi-fringe structure 1 (L=400 μm, W=4μm, no. strips=50) and the multi fringe structure 2 (L= 8 μm, W= 8μm, no. sample =1200) have been designed. These extraction methodologies show the area capacitance component, the peripheral capacitance component and the corner capacitance component at the field oxide side. The BSIM3v3 junction capacitance models are proposed also. The comparison is made to check the accuracy of the parameter models. The results showed a low level error.
DOI:10.1109/iEECON45304.2019.8938882