A Lower-Power Viterbi Decoder Design Methodology Based on Dynamic Survivor Path Decision

• Published in: 2006 International Symposium on VLSI Design, Automation and Test pp. 1 - 4
• Main Authors: Yun-Nan Chang, Yu-Chung Ding
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.04.2006
• Subjects: Computer science; Convolutional codes; Design engineering; Design methodology; Digital video broadcasting; Energy consumption; Hardware; Iterative decoding; Read-write memory; Viterbi algorithm
• ISBN: 1424401798; 9781424401796
• DOI: 10.1109/VDAT.2006.258173

In this paper, a low-power design of Viterbi decoders has been proposed based on a novel survivor path trace mechanism. By incorporating the dynamic multiple path convergence scheme, the survivor path can be determined at earlier stage such that the overall survivor memory access can be reduced. The experimental results show that the average memory reference can be reduced up to more than 30% for digital video broadcasting (DVB) application at high signal-to-noise ratio. The bit-error-rate (BER) performance of the proposed approach can be even better in some cases. This approach can lead to the reduction of power since memory operation is considered as the major power consumption of the entire decoders. An efficient VLSI architecture of Viterbi decoder for DVB standard is also presented based on the proposed design methodology. One salient feature of this architecture is that the survivor memory can be implemented by using only three single-port memory banks