FPGA implementation of LTE turbo decoder using MAX-log MAP algorithm

Implementation of an efficient turbo decoder with low complexity, short delay and insignificant performance degradation is currently a quite challenging task. The paper presents an implementation of a 3GPP TS 36.212 LTE turbo decoder. The design of the turbo decoder has been optimized to achieve eff...

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Bibliographic Details
Published in2017 6th Mediterranean Conference on Embedded Computing (MECO) pp. 1 - 4
Main Authors Belov, Vadim, Mosin, Sergey
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.06.2017
Subjects
Algorithm design and analysis
Approximation algorithms
BCJR
Computer architecture
Decoding
Field programmable gate arrays
FPGA implementation
Iterative decoding
LTE turbo decoder
MAX-log MAP
Turbo codes
Turbo decoder
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Summary:Implementation of an efficient turbo decoder with low complexity, short delay and insignificant performance degradation is currently a quite challenging task. The paper presents an implementation of a 3GPP TS 36.212 LTE turbo decoder. The design of the turbo decoder has been optimized to achieve efficient FPGA resource utilization. This design can be useful for applications, which is critical to resource utilizations, but do not need high throughput.
DOI:10.1109/MECO.2017.7977157