Modeling Effects of Interface Trap States on the Gate C-V Characteristics of MOS Devices with Ultrathin High-K Gate Dielectrics

A physically based, quantum mechanical model is presented for C-V characteristics of MOS devices with ultrathin high-K gate dielectrics including interface trap and wave function penetration effects. Numerical results show that C-V curves are rather sensitive to the details of the interface trap dis...

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Bibliographic Details
Published in2007 IEEE Conference on Electron Devices and Solid-State Circuits pp. 157 - 159
Main Authors Satter, M.M., Haque, M.A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2007
Subjects
Capacitance-voltage characteristics
CMOS technology
Dielectric substrates
Electron traps
High-K gate dielectrics
MOS devices
Poisson equations
Quantum mechanics
Voltage
Wave functions
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Summary:A physically based, quantum mechanical model is presented for C-V characteristics of MOS devices with ultrathin high-K gate dielectrics including interface trap and wave function penetration effects. Numerical results show that C-V curves are rather sensitive to the details of the interface trap distributions. The proposed model may be used for accurately extracting profiles of interface trap states from low frequency C-V measurement.
ISBN:9781424406364
1424406366
DOI:10.1109/EDSSC.2007.4450086