Impact of matched high-K gate dielectric based DG-MOSFET on SRAM performance

• Published in: 2017 4th International Conference on Power, Control & Embedded Systems (ICPCES) pp. 1 - 5
• Main Authors: Gupta, Mitashra, Nandi, Ashutosh
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.03.2017
• Subjects: 6T-SRAM; DG-MOSFET; Dielectrics; Hafnium compounds; High-K dielectric constant; High-k dielectric materials; Logic gates; MOS devices; Read access time; SRAM cells; Write access time of SRAM and Read SNM; Write SNM

The gate tunneling leakage is of paramount importance at Nano-scale technology node while designing DG-MOSFET with the thin SiO 2 gate dielectric. Therefore, replacing the gate dielectric with a physically thicker layer of High-K material is a preferred choice at this Nano-scale level. However, the...