Impact of matched high-K gate dielectric based DG-MOSFET on SRAM performance

The gate tunneling leakage is of paramount importance at Nano-scale technology node while designing DG-MOSFET with the thin SiO 2 gate dielectric. Therefore, replacing the gate dielectric with a physically thicker layer of High-K material is a preferred choice at this Nano-scale level. However, the...

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Bibliographic Details
Published in2017 4th International Conference on Power, Control & Embedded Systems (ICPCES) pp. 1 - 5
Main Authors Gupta, Mitashra, Nandi, Ashutosh
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.03.2017
Subjects
6T-SRAM
DG-MOSFET
Dielectrics
Hafnium compounds
High-K dielectric constant
High-k dielectric materials
Logic gates
MOS devices
Read access time
SRAM cells
Write access time of SRAM and Read SNM
Write SNM
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Summary:The gate tunneling leakage is of paramount importance at Nano-scale technology node while designing DG-MOSFET with the thin SiO 2 gate dielectric. Therefore, replacing the gate dielectric with a physically thicker layer of High-K material is a preferred choice at this Nano-scale level. However, the High-K gate dielectric based DG-MOSFET provides unique design challenges in terms of performance and robustness. Therefore, in the present work, we present the impact of Unmatched and Matched High-K gate dielectric based DG-MOSFET on the performance of 6T-SRAM cell. From TCAD Sentaurus mixed mode simulation results, it is observed that for same effective oxide thickness (EOT) the unmatched High-K structures show a significant deterioration of noise margins of the SRAM cell. On the other hand, the proposed matched High-K structures enhance the performance of SRAM in terms of Static Noise Margin (SNM) and access time as compared to the SiO 2 gate dielectric based DG-MOSFET.
DOI:10.1109/ICPCES.2017.8117620