Modelling and Simulation of Non-Ideal MAGIC NOR Gates on Memristor Crossbar

• Published in: 2018 8th International Symposium on Embedded Computing and System Design (ISED) pp. 124 - 128
• Main Authors: G., Naveen Murali, Lalchhandama, F., Datta, Kamalika, Sengupta, Indranil
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2018
• Subjects: 2D crossbar; Delays; Integrated circuit modeling; Logic design; Logic gates; MAGIC NOR Gate; Memristor; Memristors; Non-Ideal Model; Resistance; Switches
• ISSN: 2473-9413
• DOI: 10.1109/ISED.2018.8704015

Memristors, as a consequence of their unique properties like non-volatility, scalability, and compatibility with existing CMOS fabrication technologies, had been of key interest to the circuit designers exploring the beyond-CMOS regime. Memristors could be utilized for implementation of both memory systems and logic computational systems and hence is a promising circuit element for implementing future non-Von Neumann type architectures. Memristors fabricated onto a crossbar structure provides a scalable and robust architecture for memristor-based computational systems. However, all the works on memristorbased systems to date are based on ideal models, ignoring the process variations and parasitics that can arise in actual circuit implementations. The parasitic components like interconnect resistance and capacitance in crossbar structure play a crucial role in circuit operation as the device dimensions are scaled down into the deep sub-micron regime. Also the parameters of individual memristors, especially the Ron and Roff, of the memristors can be greatly affected by the fabrication process variations. These non-idealities are explored in this paper for the implementation of a MAGIC NOR gate on a 2D memristor crossbar. The simulation of a non-ideal MAGIC NOR gate model is presented and the observations are discussed.