Layout generation for low-power NMOS 4-phase dynamic logic array

An array cell (AC) architecture is described, which is dedicated to low-power design of NMOS 4-phase dynamic logic. This AC is constructed of (M/spl times/N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. The structure regularity of the AC contributes much toward the reducti...

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Bibliographic Details
Published inProceedings of IEEE. IEEE Region 10 Conference. TENCON 99. 'Multimedia Technology for Asia-Pacific Information Infrastructure' (Cat. No.99CH37030) Vol. 2; pp. 872 - 875 vol.2
Main Authors Furuie, M., Bao-Yu Song, Yoshida, Y., Onoye, T., Shirakawa, I.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Clocks
CMOS logic circuits
Delay
Frequency
Logic arrays
Logic functions
Logic gates
MOS devices
MOSFETs
Variable structure systems
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Summary:An array cell (AC) architecture is described, which is dedicated to low-power design of NMOS 4-phase dynamic logic. This AC is constructed of (M/spl times/N)+2 transistors so as to constitute each type of NMOS 4-phase logic gate. The structure regularity of the AC contributes much toward the reduction of the total layout area. A number of experimental results demonstrate that not only the low-power dissipation but also the high density of a logic macro can be attained by the NMOS 4-phase dynamic logic.
ISBN:0780357396
9780780357396
DOI:10.1109/TENCON.1999.818557