An integrated, multi-level synthesis system

• Published in: [1990 Proceedings] The First International Workshop on Rapid System Prototying pp. 167 - 175
• Main Authors: Pangrle, B.M., Pao-Po Hou, Owens, R.M., Irwin, M.J.
• Format: Conference Proceeding
• Language: English
• Published: IEEE Comput. Soc 1990
• Subjects: Clocks; Computer architecture; Computer science; Control system synthesis; Delay estimation; Libraries; Registers; Space exploration; Synthesizers; Very large scale integration
• ISBN: 9780818621758; 0818621753
• DOI: 10.1109/IWRSP.1990.144054

Outlines an integrated, multi-level VLSI synthesis system. First, an architectural synthesis tool is used to compile the high level behavioral specification of the target architecture into a register transfer level specification. Constraints are supplied as inputs to allow the user to selectively explore various portions of the design space. The goal is to let the user perform global design tradeoffs, while the system synthesizes the best designs that meet the user's constraints. Once the register transfer level description has been synthesized, the data path and control path are separated and control logic synthesis is performed. Boolean library descriptions of various components which have been presynthesized with a multi-level logic synthesis tool are used to construct the data path. Finally a gate matrix module generator is used to produce layout. With the availability of these low level synthesis tools, the high level architectural system need not rely on just estimates of delay, area, and power metrics for quantifying design alternatives.< >