Can test length be reduced during synthesis process?

Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-...

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Bibliographic Details
Published in[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design pp. 57 - 62
Main Authors De, K., Banerjee, P.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1991
Subjects
Circuit faults
Circuit synthesis
Circuit testing
Combinational circuits
Costs
Electrical fault detection
Fault detection
Logic circuits
Logic testing
System testing
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Summary:Conventional multi-level logic synthesis is targeted to reduce the area of the logic circuits (estimated via literal count). This paper looks at multi-level combinational logic synthesis from the objective of minimizing test length, i.e. the size of a test set to detect all irredundant single stuck-at faults in the circuit. The length of a test set affects the test application cost. The synthesis process has been modified to obtain circuits that can be tested with smaller test length. Results of the implementation have shown significant reduction in test length with little increase in run time over the MIS-II synthesis system and very little increase in literal count.< >
ISBN:9780818621253
0818621257
DOI:10.1109/ISVD.1991.185093