A scan-based BIST technique using pair-wise compare of identical components

Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significa...

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Bibliographic Details
Published in[1991] Proceedings. Fourth CSI/IEEE International Symposium on VLSI Design pp. 225 - 230
Main Authors Nadeau-Dostie, B., Wilcox, P.S., Agarwal, V.K.
Format Conference Proceeding
LanguageEnglish
Published IEEE Comput. Soc. Press 1991
Subjects
Application specific integrated circuits
Automatic testing
Backplanes
Built-in self-test
Circuit testing
Integrated circuit testing
Printed circuits
Random access memory
System testing
Vehicles
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Summary:Addresses the problem of efficiently testing scannable ASICs in a board-level and system-level environment. The method makes use of a serial testability bus (ETM or IEEE 1149.1) and takes advantage of the presence of identical components on the boards. The main benefits of the method are a significant reduction in test time and test data to be stored. Results obtained for an actual system show a reduction in test time of about 20 times for a module with 50 ASICs. The extra board area required was less than 2% for all boards of the module.< >
ISBN:9780818621253
0818621257
DOI:10.1109/ISVD.1991.185121