VHDL description and high-level synthesis of an ATM layer circuit

In order to manage the higher complexity of VLSI chips and to reach shorter design cycles, the design effort becomes increasingly focused on higher levels of abstraction. We describe the design and the modeling of a high speed telecommunication circuit, an ATM Switch Controller (ASC) using a behavio...

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Bibliographic Details
Published inProceedings 25th EUROMICRO Conference. Informatics: Theory and Practice for the New Millennium Vol. 1; pp. 519 - 525 vol.1
Main Authors Lange, W., Rosenstiel, W.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Asynchronous transfer mode
Circuit simulation
Circuit synthesis
Design methodology
High level synthesis
Switches
Switching circuits
Telecommunication control
Telecommunication switching
Very large scale integration
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Summary:In order to manage the higher complexity of VLSI chips and to reach shorter design cycles, the design effort becomes increasingly focused on higher levels of abstraction. We describe the design and the modeling of a high speed telecommunication circuit, an ATM Switch Controller (ASC) using a behavioral VHDL description. The VHDL description is simulated and synthesized with a commercially available High-Level Synthesis (HLS) tool. Advantages of this design method are discussed and the results of the synthesis are presented.
ISBN:9780769503219
0769503217
ISSN:1089-6503
2376-9505
DOI:10.1109/EURMIC.1999.794520