An ultra high speed ECL-bipolar CMOS technology with silicon fillet self-aligned contacts

An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion...

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Published in1992 Symposium on VLSI Technology Digest of Technical Papers pp. 30 - 31
Main Authors Liu, T.M., Chin, G.M., Morris, M.D., Jeon, D.Y., Archer, V.D., Kim, H.H., Cerullo, M., Lee, K.F., Sung, J.M., Lau, K., Chiu, T.Y., Voshchenkov, A.M., Swartz, R.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1992
Subjects
BiCMOS integrated circuits
Bipolar transistors
Capacitance
CMOS technology
Delay
Electrodes
Isolation technology
MOSFETs
Silicon
Very large scale integration
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Summary:An ultra-high-speed half-micron non-overlapped super self-aligned BiCMOS technology that uses a silicon fillet self-aligned contact technology (SIFT) for both bipolar and MOS transistors is discussed. The SIFT process reduces the device capacitances and series resistances by minimizing the diffusion region area as well as the polysilicon electrode area. Deep trench isolation for bipolar transistors allows the device area to be much reduced for VLSI applications. The ECL gate delay is demonstrated to be 31 ps for devices with emitter polysilicon widths of 0.6 mu m. The CMOS ring oscillator gate delays are 58 ps for 0.5- mu m gate length and 67 ps for 0.6- mu m gate length at 5 V.< >
ISBN:0780306988
9780780306981
DOI:10.1109/VLSIT.1992.200631