3-D stacking using the GE high density multichip module technology

• Published in: Workshop on MCM and VLSI Packaging Techniques and Manufacturing Technologies pp. 2_15 - 2_16
• Main Authors: Fillion, R.A., Saia, R., Wojnarowski, R.J., Forman, G.A., Gorowitz, B.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1994
• Subjects: Delay; Fabrication; Integrated circuit interconnections; Multichip modules; Packaging; Performance loss; Power system interconnection; Research and development; Rivers; Stacking
• DOI: 10.1109/WPTMT.1994.763543

The GE Corporate Research and Development Center has developed a 3-D stacked multichip module (MCM) technology to solve the interconnect and packaging problems associated with large distributed processing systems and of mass memory systems. The driving forces behind the development of three-dimensional packaging technology include the promise of significant size and weight reductions, higher performance (increased operating rates and reduced delays), higher reliability and, potentially, reduced power dissipation. If the chips are separated by large parasitics and long delays, then the interaction of a group of chips will be degraded. The performance loss due to the chip-to-chip delays is worse with higher performance chips and with slower chip-to-chip communication paths. High speed chip sets in the 100 MHz range, can have 50% or more of the circuit cycle time tied to interconnection delays.