A four-level-metal fully planarized interconnect technology for dense high performance logic and SRAM applications

The authors describe a four-level-metal (4LM) interconnect technology used to wire high-density, high-performance logic and SRAM chip designs. Process features includes oxide planarization under all metal levels, tungsten studs for contacts and interlevel vias, layered titanium and aluminium-0.5% co...

Full description

Saved in:
Bibliographic Details
Published in1991 Proceedings Eighth International IEEE VLSI Multilevel Interconnection Conference pp. 20 - 26
Main Authors Uttecht, R.R., Geffken, R.M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1991
Subjects
Copper
Etching
Integrated circuit interconnections
Logic design
Planarization
Redundancy
SRAM chips
Titanium
Tungsten
Wire
Online AccessGet full text

Cover

More Information
Summary:The authors describe a four-level-metal (4LM) interconnect technology used to wire high-density, high-performance logic and SRAM chip designs. Process features includes oxide planarization under all metal levels, tungsten studs for contacts and interlevel vias, layered titanium and aluminium-0.5% copper metal lines patterned by reactive ion etch (RIE), and fusible metal links for redundancy applications. Functional 300K circuit ASIC logic test sites (4LM) and 256K SRAMs (3LM) have been fabricated in both 125-mm and 200-mm wafer sizes. Process details are described along with the results of standard electrical tests and reliability stresses.< >
ISBN:087942673X
9780879426736
DOI:10.1109/VMIC.1991.152961