Degradation of MOS transistor characteristics By gate charging damage during plasma processing

• Published in: 1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers pp. 320 - 324
• Main Authors: Chang, M.C., Wu, C.Y., Lin, G.L., Liao, I.C., Lee, Y.H., Chen, C.N.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1993
• Subjects: Alloying; Degradation; Electrodes; Electrostatic discharge; Interface states; MOSFETs; Plasma applications; Plasma materials processing; Plasma properties; Stress
• ISBN: 0780309782; 9780780309784
• ISSN: 1524-766X; 2690-8174
• DOI: 10.1109/VTSA.1993.263671

The plasma-induced charge damage to small gate area MOS transistors is investigated by using different 'antenna' structures and forming gas alloying process. The plasma processes before metal 2 alloy induce negative charges in the gate electrode, resulting in the generation of the positive charge traps in the gate oxide. The plasma processes from the deposition plasma-enhanced oxide passivation film and its etching induce positive charges in the gate electrode that result in the generation of the interface states and negative charge traps in the gate oxide region due to electrostatic discharges. These phenomena have been evidenced by using different antenna ratios and layout structures. At the same time, the degree of oxide damage is proportional to the antenna ratio. The interface states and charge trapping in gate oxide can be annealed out by the alloying process, but it can be easily regenerated by the constant current stress. The ESD or diode protection structures can reduce the gate charging damages during the plasma processing step, and the trap generation rate is also lower than the unprotected structures during the constant current stress.< >