Performance optimization of a high speed super self-aligned BiCMOS technology

The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, f/sub max/, has been increased from 25.9 GHz to 33.5 GHz. Since all the...

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Bibliographic Details
Published in1993 International Symposium on VLSI Technology, Systems, and Applications Proceedings of Technical Papers pp. 297 - 300
Main Authors Liu, T.M., Chin, G.M., Morris, M.D., Jeon, D.Y., Johnson, R.W., Archer, V.D., Tarsia, M.J., Kim, H.H., Cerullo, M., Lee, K.F., Sung, J.M., Lau, K., Feuer, M.D., Voshchenkov, A.M., Swartz, R.G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1993
Subjects
BiCMOS integrated circuits
Bipolar transistors
Capacitance
CMOS memory circuits
CMOS process
CMOS technology
Cutoff frequency
Delay
MOS devices
Optimization
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Summary:The authors present the process optimization and device characteristics of a half-micron super self-aligned BiCMOS technology. With a new emitter/base process in their BiCMOS flow, bipolar transistor power gain cutoff frequency, f/sub max/, has been increased from 25.9 GHz to 33.5 GHz. Since all the process parameters related to CMOS are kept constant, high speed CMOS circuit operation is maintained without compromise. The measured nominal CMOS gate delay with a gate length of 0.5 mu m is 47 psec at 5V and 54 psec at 3.3V.< >
ISBN:0780309782
9780780309784
ISSN:1524-766X
2690-8174
DOI:10.1109/VTSA.1993.263666