High flexibility CMOS SRAM generator using multiplan architecture

This paper presents a high flexibility CMOS SRAM generator design methodology. The concept of flexibility space is defined and a new merit factor for memory array generators is proposed. A self-timed form factor adaptative controller sequences the memory operations to potentially generate 30000 memo...

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Bibliographic Details
Published inTwelfth Annual IEEE International ASIC/SOC Conference (Cat. No.99TH8454) pp. 414 - 417
Main Authors Clerc, S., Dufourt, D., Zangara, L.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Amplitude shift keying
Automatic generation control
Clocks
Decoding
Design methodology
Design optimization
Random access memory
System-on-a-chip
Temperature distribution
Testing
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Summary:This paper presents a high flexibility CMOS SRAM generator design methodology. The concept of flexibility space is defined and a new merit factor for memory array generators is proposed. A self-timed form factor adaptative controller sequences the memory operations to potentially generate 30000 memory configurations. Critical memory configurations are isolated and simulated to validate the design. A reference memory configuration featuring 2k/spl times/16 bits has been fabricated using a 0.35 /spl mu/m CMOS process. The chip has 1350/spl times/1570 /spl mu/m dimensions and operates at 100 MHz over a 5.5 V to 2.0 V supply range.
ISBN:9780780356320
0780356322
DOI:10.1109/ASIC.1999.806546