Test ready core design for TeakLite core

• Published in: AP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) pp. 363 - 366
• Main Authors: Heemin Park, Gyoochan Sim, Jaehoon Jung, Hong-Shin Jun
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1999
• Subjects: Application specific integrated circuits; Circuit testing; Clocks; Consumer electronics; Degradation; Digital signal processing; Large scale integration; Logic testing; Pins; System-on-a-chip

This paper describes test ready core design methodology for TeakLite core. Implementation issues and techniques about test access with minimal test pins, scan chain reconfiguration, and UDL test capability are presented. Testability enhancement for development of high quality test vector is also des...