Test ready core design for TeakLite core

This paper describes test ready core design methodology for TeakLite core. Implementation issues and techniques about test access with minimal test pins, scan chain reconfiguration, and UDL test capability are presented. Testability enhancement for development of high quality test vector is also des...

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Published inAP-ASIC'99. First IEEE Asia Pacific Conference on ASICs (Cat. No.99EX360) pp. 363 - 366
Main Authors Heemin Park, Gyoochan Sim, Jaehoon Jung, Hong-Shin Jun
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Application specific integrated circuits
Circuit testing
Clocks
Consumer electronics
Degradation
Digital signal processing
Large scale integration
Logic testing
Pins
System-on-a-chip
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Summary:This paper describes test ready core design methodology for TeakLite core. Implementation issues and techniques about test access with minimal test pins, scan chain reconfiguration, and UDL test capability are presented. Testability enhancement for development of high quality test vector is also described. As the result, a very high fault coverage of 99.68% has been achieved. We also present the features of test ready TeakLite core.
ISBN:0780357051
9780780357051
DOI:10.1109/APASIC.1999.824107