Architecture and performance of 3-dimensional SOI circuits

In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.

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Bibliographic Details
Published in1999 IEEE International SOI Conference. Proceedings (Cat. No.99CH36345) pp. 44 - 45
Main Authors Rongtian Zhang, Roy, K., Janes, D.B.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1999
Subjects
Buildings
Circuit optimization
Circuit synthesis
CMOS technology
Costs
Integrated circuit interconnections
Semiconductor device measurement
Silicon on insulator technology
Size measurement
Wire
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Summary:In this paper, potential three-dimensional SOI CMOS VLSI circuit structures are laid out. Chip area, layout complexities, process costs, and impact on circuit performance are compared and discussed.
ISBN:9780780354562
0780354567
ISSN:1078-621X
2577-2295
DOI:10.1109/SOI.1999.819850