Design and benchmarking of BCPMOS versus SCPMOS for an evolutionary 0.25-/spl mu/m CMOS technology

TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub D...

Full description

Saved in:
Bibliographic Details
Published inIEEE transactions on electron devices Vol. 45; no. 4; pp. 991 - 993
Main Authors Vuong, H.-H., Eshraghi, S.A., Rafferty, C.S., Hillenius, S.J., Pinto, M.R., Diodato, P.W., Cong, H.-I., Zeitzoff, P.M.
Format Journal Article
LanguageEnglish
Published IEEE 01.04.1998
Subjects
Circuit optimization
CMOS technology
Delay
Design optimization
Implants
Inverters
Manufacturing processes
Semiconductor device modeling
Switches
Threshold voltage
Online AccessGet full text

Cover

More Information
Summary:TCAD tools were used to design and benchmark 0.25-/spl mu/m buried-channel PMOS (BCPMOS) versus surface-channel PMOS (SCPMOS), for both device and circuit performance. With optimized device designs, BCPMOS gives smaller gate delays than SCPMOS for INVERTER and NAND gates with supply voltages V/sub DD/>1.4 V, and for NOR gates with V/sub DD/>2.4 V.
ISSN:0018-9383
1557-9646
DOI:10.1109/16.662818