An approach to placement-coupled logic replication

• Published in: Proceedings. 41st Design Automation Conference, 2004 pp. 711 - 716
• Main Authors: Hrkic, M., Lillis, J., Beraudo, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2004
• Subjects: Circuits; Computer science; Cost function; Delay; Engines; Field programmable gate arrays; Permission; Programmable logic arrays; Programmable logic devices; Tree graphs
• ISBN: 1511838288
• ISSN: 0738-100X
• DOI: 10.1109/DAC.2004.240527

We present a set of techniques for placement-coupled, timing driven logic replication. Two components are at the core of the approach. First is an algorithm for optimal timing driven fanin tree embedding; the algorithm is very general in that it can easily incorporate complex objective functions (e.g., placement costs) and can perform embedding on any graph-based target. Second we introduce the Replication nee which allows us to induce large fanin trees from a given circuit which can then be optimized by the embedder. We have built an optimization engine around these two ideas and report promising results for the FPGA domain including clock period reductions of up to 36% compared with a timing-driven placement from VPR [12] and almost double the average improvement of local replication from [I]. These results are azhieved with modest area and runtime overhead.