Electrical Optimization of PLAs

• Published in: 22nd ACM/IEEE Design Automation Conference pp. 681 - 687
• Main Author: Hedlund, K.S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1985
• Subjects: Circuits; Computer science; Delay estimation; Design optimization; Energy consumption; Minimization methods; MOS devices; Programmable logic arrays; Prototypes; Topology
• ISBN: 0818606355; 9780818606359
• ISSN: 0738-100X
• DOI: 10.1109/DAC.1985.1586016

This work addresses the problem of improving an nMOS PLA's speed and power consumption through modifications to the transistor sizes in the PLA. A simplified model of gate delay (lumped RC model) is used that allows rapid estimation of delays thus allowing interactive computation of optimal transistor sizes. Algorithms are presented for: a) minimization of delay through the PLA b) minimization of power consumption subject to a bound on maximum delay. Both these minima are computed subject to bounds on the transistor sizes. A prototype electrical optimization tool was compared to the PLA generation tools in the Berkeley CAD tools package (eqntott and tpla). The maximum delay through a PLA can often be reduced by a factor of 2, and power consumption along the critical paths can be reduced by 10 - 30% without increasing maximum delay.