Automated timing model generation

The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the...

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Bibliographic Details
Published inProceedings 2002 Design Automation Conference (IEEE Cat. No.02CH37324) pp. 146 - 151
Main Authors Daga, A.J., Mize, L., Sripada, S., Wolff, C., Qiuyang Wu
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Algorithm design and analysis
Application software
Electronic design automation and methodology
Intellectual property
Libraries
Performance analysis
Permission
Runtime
System-on-a-chip
Timing
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Summary:The automated generation of timing models from gate-level netlists facilitates IP reuse and dramatically improves chip-level STA runtime in a hierarchical design flow. In this paper we discuss two different approaches to model generation, the design flows they lend themselves to and results from the application of these model generation solutions to large customer designs.
ISBN:1581134614
9781581134612
ISSN:0738-100X
DOI:10.1109/DAC.2002.1012610