Design of oversampling current steering DAC with 640 MHz equivalent clock frequency

Recent mobile communications demand high-speed and high-resolution data converters for digital signal processing (DSP) in the receiver and transceiver of the communication systems. Those applications require more than 14-bit resolution and several hundred of MHz bandwidth. In this paper, we propose...

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Bibliographic Details
Published in2002 IEEE International Symposium on Circuits and Systems (ISCAS) Vol. 1; p. I
Main Authors Yunyoung Choi, Maloberti, F.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2002
Subjects
Bandwidth
Circuits
Clocks
Delta-sigma modulation
Digital signal processing
Digital-analog conversion
Frequency conversion
Mobile communication
Signal resolution
Transceivers
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Summary:Recent mobile communications demand high-speed and high-resolution data converters for digital signal processing (DSP) in the receiver and transceiver of the communication systems. Those applications require more than 14-bit resolution and several hundred of MHz bandwidth. In this paper, we propose a new sigma-delta parallel DAC (Digital-to-Analog Converter) structure that achieves the required accuracy with 640 MHz clock frequency. The circuit employs current steering and multi-bit solution with matching technique. The entire architecture has been verified by simulations with a 0.18 /spl mu/m CMOS process (TI).
ISBN:9780780374485
0780374487
DOI:10.1109/ISCAS.2002.1009789