Structure and metrology for an analog testability bus

This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4. The proposed testability structure is imposed on the I/O pin cells of the analog and mixed technology ICs. It is a superset of the existing IEEE/ANSI 1149.1 testability stan...

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Bibliographic Details
Published inProceedings of IEEE International Test Conference - (ITC) pp. 309 - 317
Main Authors Parker, K.P., McDermid, J.E., Oresjo, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1993
Subjects
Analog integrated circuits
Circuit testing
Digital integrated circuits
Integrated circuit interconnections
Manufacturing
Metrology
Pins
Software standards
Software testing
Wires
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Summary:This paper gives a proposal for an analog testability bus that could be used as the basis for a standard such as IEEE P1149.4. The proposed testability structure is imposed on the I/O pin cells of the analog and mixed technology ICs. It is a superset of the existing IEEE/ANSI 1149.1 testability standard for digital ICs and is intended to cooperate with it. This allows for the testing of interconnect failures such as shorts and opens, the testing of discrete analog components and networks between ICs, and supports the testing of analog functions within the ICs themselves. This paper is a companion to the result of a cooperative effort between AT&T, Ford Motor, Hewlett-Packard, Motorola and the University of Colorado at Colorado Springs.< >
ISBN:0780314301
9780780314306
DOI:10.1109/TEST.1993.470682