KaGen-A generator of static CMOS-cell layout from circuit schematics

KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a...

Full description

Saved in:
Bibliographic Details
Published in1993 IEEE International Symposium on Circuits and Systems (ISCAS) pp. 1845 - 1848 vol.3
Main Authors Doerffer, K., Teby, A.T., Anton, O., Mlynski, D.A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.05.1993
Subjects
Algorithm design and analysis
CMOS logic circuits
Collision mitigation
Digital signal processing
Minimization methods
Neodymium
Partitioning algorithms
Strips
Variable structure systems
Online AccessGet full text

Cover

More Information
Summary:KaGen is a layout generator of functional CMOS cells from circuit schematics. It aims at cell height and width optimization. It is capable of generating cells not only for dual series-parallel CMOS circuits, but also for non-dual and non-series-parallel circuits (for example any circuit containing a transfer gate). The system operates in three stages. The circuit is positioned into subcircuits. For each subcircuit, a set of layout-candidates for an optimal cell is generated. In the last step, the cells are placed. During placement, the best fitting cells are chosen from the set of layout-candidates.< >
ISBN:9780780312814
0780312813
DOI:10.1109/ISCAS.1993.394106