Architecture and performance of an electro-optical high speed packet switch

A high speed packet switch based on VLSI chips and optical components is presented. The chips, located at the inputs of the switch, implement the routing algorithm, store the incoming packets, and control the access to the optical interconnection network, which connects inputs and outputs. The simul...

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Bibliographic Details
Published inIEEE TENCON'90: 1990 IEEE Region 10 Conference on Computer and Communication Systems. Conference Proceedings pp. 541 - 545 vol.2
Main Author Albertengo, G.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1990
Subjects
High speed optical techniques
Logic functions
Optical devices
Optical interconnections
Optical packet switching
Optical receivers
Optical switches
Optical transmitters
Packet switching
Very large scale integration
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Summary:A high speed packet switch based on VLSI chips and optical components is presented. The chips, located at the inputs of the switch, implement the routing algorithm, store the incoming packets, and control the access to the optical interconnection network, which connects inputs and outputs. The simulation showed that up to two packets at a time must be transmitted on the optical interconnection network from any input to achieve optimal performance. The impact of this result on the chip complexity and on the transmission scheme used in the optical part is discussed, and a possible solution is outlined.< >
ISBN:9780879425562
0879425563
DOI:10.1109/TENCON.1990.152668