Estimation of maximum transition counts at internal nodes in CMOS VLSI circuits

• Published in: Proceedings of IEEE International Conference on Computer Aided Design (ICCAD) pp. 366 - 370
• Main Authors: Chin-Chi Teng, Hill, A.M., Sung-Mo Kang
• Format: Conference Proceeding
• Language: English
• Published: IEEE 1995
• Subjects: Circuit simulation; Combinational circuits; Delay effects; Energy consumption; Integrated circuit reliability; Switches; Switching circuits; Uncertainty; Upper bound; Very large scale integration
• ISBN: 0818682000; 0818672137; 9780818672132; 9780818682001
• ISSN: 1063-6757; 1092-3152; 1558-2434
• DOI: 10.1109/ICCAD.1995.480142

In combinational logic circuits, a single switching event on the primary inputs may give rise to multiple switchings at the internal nodes. This glitching effect is caused primarily by unequal delay paths and results in increased power consumption and decreased device reliability. In this paper, we present a new algorithm to estimate the maximum number of transitions at internal nodes in combinational CMOS VLSI circuits. Unlike exhaustive simulation, our algorithm is based on the technique of propagating uncertainty waveforms throughout the circuit and using these waveforms to count the maximum switching activity at every node. Our approach guarantees a tight upper bound on the number of transitions which is necessary to assess the minimum circuit reliability lifetime and maximum power dissipation.