Parallel model evaluation for circuit simulation on the PACE multiprocessor

Device model evaluation, an essential part of a circuit simulator, is a compute-intensive task. A multiprocessor-based circuit simulator that ignores the parallelization of model equation formulation (LOAD), and just parallelizes the solution (SOLVE) of the equations will seriously degrade the simul...

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Bibliographic Details
Published inProceedings of 7th International Conference on VLSI Design pp. 45 - 48
Main Authors Agrawal, P., Goil, S., Liu, S., Trotter, J.A.
Format Conference Proceeding
LanguageEnglish
Published IEEE 1994
Subjects
Circuit simulation
Computational modeling
Coupling circuits
Degradation
Differential equations
Jacobian matrices
Legged locomotion
Nonlinear equations
Parallel architectures
Predictive models
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Summary:Device model evaluation, an essential part of a circuit simulator, is a compute-intensive task. A multiprocessor-based circuit simulator that ignores the parallelization of model equation formulation (LOAD), and just parallelizes the solution (SOLVE) of the equations will seriously degrade the simulation performance. This paper describes methods of parallelizing the LOAD part of a circuit simulator on PACE (Parallel Architecture for Circuit Evaluation) a distributed memory multiprocessor designed at AT&T Bell Laboratories. This is integrated with the parallel SOLVE algorithms given in our earlier work. Load balancing and minimization of interprocessor communication are used as the primary objectives of the parallel LOAD heuristics studied. Performance results, using the prototype PACE system, on benchmark circuits show the feasibility of our approach.< >
ISBN:9780818649905
0818649909
ISSN:1063-9667
2380-6923
DOI:10.1109/ICVD.1994.282653