Current steering high-speed DAC: architecture analysis and simulation results

A DAC architecture based on the current steering method is presented. The proposed architecture exploits the oversampling and uses a MASH like configuration. The DAC requires to use two current steering 5-bit D/A converters whose current references are properly scaled. The two output currents are su...

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Bibliographic Details
Published inProceedings of the IEEE 2nd Dallas CAS Workshop on Low Power/Low Voltage Mixed-Signal Circuits & Systems (DCAS-01) (Cat. No.01EX454) pp. P27 - P30
Main Authors Yunyoung Choi, Franco, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2001
Subjects
3G mobile communication
Analytical models
Bandwidth
Base stations
Clocks
Delta-sigma modulation
Frequency
GSM
Multi-stage noise shaping
Noise shaping
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Summary:A DAC architecture based on the current steering method is presented. The proposed architecture exploits the oversampling and uses a MASH like configuration. The DAC requires to use two current steering 5-bit D/A converters whose current references are properly scaled. The two output currents are summed at the output node to achieve the output signal. With an oversampling factor equal to 8 and 40 MHz band-width (clock frequency 640 MHz) it is possible to reach an SNR as large as 72 dB.
ISBN:9780780366244
0780366247
DOI:10.1109/DCAS.2001.920988