Digital timing synchronization with jitter reduction technique for cap-based VDSL system

• Published in: 2001 IEEE International Conference on Acoustics, Speech, and Signal Processing. Proceedings (Cat. No.01CH37221) Vol. 4; pp. 2325 - 2328 vol.4
• Main Authors: Yongchul Song, Kyehyung Lee, Beomsup Kim
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2001
• Subjects: Adaptive control; Adaptive filters; Adaptive systems; CMOS technology; Digital control; Digital filters; Performance gain; Programmable control; Steady-state; Timing jitter
• ISBN: 0780370414; 9780780370418
• ISSN: 1520-6149; 2379-190X
• DOI: 10.1109/ICASSP.2001.940465

This paper describes a digital timing synchronization method for the CAP-based VDSL system. An adaptive loop filter with digitally controlled loop gain is proposed for jitter performance improvement. The proposed loop filter allows both fast locking and low steady state jitter. A digital spectral line method is used for robust timing extraction. Simulation results show that RMS timing jitter is less than 0.4% of the symbol period even for the worst case channel and synchronization is established within 400 symbol periods. The VDSL system is implemented in a 0.6 /spl mu/m CMOS technology, and tested. The measured peak-to-peak timing jitter is about 0.1% of the symbol period, which makes the VDSL system receive data up to 52 Mbps over the telephone wire.