27.2 14.1-ENOB 184.9dB-FoM Capacitor-Array-Assisted Cascaded Charge-Injection SAR ADC

• Published in: 2021 IEEE International Solid- State Circuits Conference (ISSCC) Vol. 64; pp. 372 - 374
• Main Authors: Choo, Kyojin, An, Hyochan, Sylvester, Dennis, Blaauw, David
• Format: Conference Proceeding
• Language: English
• Published: IEEE 13.02.2021
• Subjects: Energy efficiency; Energy resolution; Sensors; Signal resolution; Signal sampling; Signal to noise ratio; Solid state circuits
• ISSN: 2376-8606
• DOI: 10.1109/ISSCC42613.2021.9365863

IoT sensors are in rising demand and they often require low power, yet high precision measurements. Under constrained energy, Nyquist-rate SAR ADCs are typically used for readout as they are energy efficient and easy to multiplex across many sensors. However, achieving high precision (>14b) in SAR ADCs is challenging as all factors limiting performance (resolution, mismatch, and noise) must be simultaneously addressed with minimal energy impact. In this paper, we present an energy-efficient, capacitor-array-assisted cascaded charge-injection SAR ADC (c-ciSAR) with 17b nominal resolution (14.14b ENOB) that achieves a 184.9dB Schreier FoM (SFoM) and 4.32fJ/conv with a 1V supply in 0.18μm CMOS. The ADC deploys a combination of techniques to improve resolution, mismatch, and noise performance while remaining energy-efficient, namely: 1) hybridization of a capacitor-array DAC (CDAC) with chargeinjection-cell (ci-cell) based DACs (ciDACs) to achieve high resolution and flexible programmability; 2) direct analog DAC mismatch compensation and repeated LSB decisions that leverage flexible programmability; 3) a noise-efficient charge-domain preamplifier for comparator (1.66 NEF) and SNR extended ci-cell; and 4) ±2?VDD signal sampling with pre-sampling MSB decision.