Demonstration of scaled 0.099µm2 FinFET 6T-SRAM cell using full-field EUV lithography for (Sub-)22nm node single-patterning technology

• Published in: 2009 IEEE International Electron Devices Meeting (IEDM) pp. 1 - 4
• Main Authors: Veloso, A., Demuynck, S., Ercken, M., Goethals, A.M., Locorotondo, S., Lazzarino, F., Altamirano, E., Huffman, C., De Keersgieter, A., Brus, S., Demand, M., Struyf, H., De Backer, J., Hermans, J., Delvaux, C., Baudemprez, B., Vandeweyer, T., Van Roey, F., Baerts, C., Goossens, D., Dekkers, H., Ong, P., Heylen, N., Kellens, K., Volders, H., Hikavyy, A., Vrancken, C., Rakowski, M., Verhaegen, S., Dusa, M., Romijn, L., Pigneret, C., Van Dijk, A., Schreutelkamp, R., Cockburn, A., Gravey, V., Meiling, H., Hultermans, B., Lok, S., Shah, K., Rajagopalan, R., Gelatos, J., Richard, O., Bender, H., Vandenberghe, G., Beyer, G.P., Absil, P., Hoffmann, T., Ronse, K., Biesemans, S.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 01.12.2009
• Subjects: Contacts; Costs; Filling; FinFETs; High K dielectric materials; High-K gate dielectrics; Lithography; Metallization; Random access memory; Silicides
• ISBN: 9781424456390; 1424456398
• ISSN: 0163-1918; 2156-017X
• DOI: 10.1109/IEDM.2009.5424365

We demonstrate electrically functional 0.099 μm 2 6T-SRAM cells using full-field EUV lithography for contact and M1 levels. This enables formation of dense arrays without requiring any OPC/RET, while exhibiting substantial process latitudes & potential lower cost of ownership (single-patterning). Key enablers include: 1) high-k/metal gate FinFETs with L g ˜40 nm, 12-17 nm wide Fins, and cell β ratio ˜1.3; 2) option for using an extension-less approach, advantageous for reducing complexity with 2 less I/I photos, and for enabling a better quality, defect-free growth of Si-epitaxial raised S/D; 3) use of double thin-spacers and ultra-thin silicide; 4) optimized W metallization for filling high aspect-ratio, ⩾30 nm-wide contacts. SRAM cell with SNM≫10%V DD down to 0.4V, and healthy electrical characteristics for the cell transistors [SS˜80 mV/dec, DIBL˜50-80 mV/V, and |V Tlin |⩾0.2 V (PMOS), V Tlin ˜0.36 V (NMOS)] are reported.