An Algorithm for Gate Resizing to Reduce Power Dissipation in Combinational Digital Designs

Large gates are fast but dissipate more power compared to small ones. To satisfy timing constraints, large gates can be used on critical paths while small ones can be used elsewhere. In this paper, we address the problem of assigning small gates on non-critical paths under timing constraints. This p...

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Bibliographic Details
Published in2022 IEEE 3rd International Conference on Electronics, Control, Optimization and Computer Science (ICECOCS) pp. 1 - 3
Main Authors Chabini, Noureddine, Belkouch, Said, Najoui, Mohamed
Format Conference Proceeding
LanguageEnglish
Published IEEE 01.12.2022
Subjects
Approximation algorithms
area
C languages
Capacitance
CMOS technology
Computer science
digital combinational designs
Logic gates
Power dissipation
timings
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Summary:Large gates are fast but dissipate more power compared to small ones. To satisfy timing constraints, large gates can be used on critical paths while small ones can be used elsewhere. In this paper, we address the problem of assigning small gates on non-critical paths under timing constraints. This problem is NP-hard. We propose a heuristic to solve it.
DOI:10.1109/ICECOCS55148.2022.9982942