Group-Chopping: An 8-Channel, 0.04% Gain Mismatch, 2.1 µW 0.017 mm2 Instrumentation Amplifier for Bio-Potential Recording

• Published in: IEEE transactions on biomedical circuits and systems Vol. 16; no. 3; pp. 361 - 371
• Main Authors: Tang, Tao, Park, Jeong Hoan, Zhang, Lian, Ng, Kian Ann, Yoo, Jerald
• Format: Journal Article
• Language: English
• Published: New York IEEE 01.06.2022; The Institute of Electrical and Electronics Engineers, Inc. (IEEE)
• Subjects: Amplification; Amplifiers; Analog Front-End (AFE); between-channel CMRR (CMRR<named-content xmlns:xlink="http://www.w3.org/1999/xlink" xmlns:ali="http://www.niso.org/schemas/ali/1.0/" xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xsi="http://www.w3.org/2001/XMLSchema-instance" content-type="math" xlink:type="simple"> <inline-formula> <tex-math notation="LaTeX"> _{\text{btw-chn}}</tex-math> </inline-formula> </named-content>); bio-recording AFE; Biomedical monitoring; Channels; chopper-stabilizat- ion; Cutting; Electrocardiography; Electrodes; Electroencephalography; Gain; gain mismatch; group-chopping; Instrumentation; instrumentation amplifier; Instruments; multi-channel gain mismatch mitigation; Recording; Switches
• ISSN: 1932-4545; 1940-9990
• DOI: 10.1109/TBCAS.2022.3166513

An 8-channel AFE with a group-chopping instrumentation amplifier (GCIA) is proposed for bio-potential recording applications. The group-chopping technique cascades chopper switches to progressively swap channels and dynamically removes gain mismatch among all channels. An 8-phase non-overlapping clocking scheme is developed and achieves excellent between-channel gain mismatch characteristics. The dynamic offsets among all channels are mitigated by the GCIA as well. The GCIA is the first work that minimizes the gain mismatch across more than two channels. With the help of the group-chopping, combined with an area-efficient open-loop structure, the GCIA shows <0.04% between-channel gain mismatch, the lowest mismatch reported to date. The chip is fabricated in 0.18µm 1P6M CMOS, occupies only 0.017 mm 2 /Ch., consumes 2.1 μW/Ch. under 0.5 V supply and achieves an NEF of 2.1.