High speed synchronization module implemented in altera stratix II FPGA

This paper presents programmable FPGA-based divider of high frequency reference signal dedicated to generate various frequencies for synchronization of particle accelerator subsystems. The digital circuit was synthesized using pure VHDL description thus can be implemented not only in target Altera S...

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Bibliographic Details
Published inProceedings of the International Conference Mixed Design of Integrated Circuits and System, 2006. MIXDES 2006 pp. 69 - 72
Main Authors Przygoda, K., Grecki, M.
Format Conference Proceeding
LanguageEnglish
Published IEEE 2006
Subjects
Circuits
Clocks
Field programmable gate arrays
Frequency conversion
Frequency synchronization
Multiplexing
Particle accelerators
Radio frequency
RF signals
Signal generators
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Summary:This paper presents programmable FPGA-based divider of high frequency reference signal dedicated to generate various frequencies for synchronization of particle accelerator subsystems. The digital circuit was synthesized using pure VHDL description thus can be implemented not only in target Altera Stratix II high-speed FPGA chip but other FPGAs as well. The implemented circuit operates up to the FPGA frequency limit of 500 MHz. The generated frequency signals can be time shifted by programmable multiplicity of the clock period (2ps) without introducing additional phase skew to the output signals
ISBN:9788392263227
8392263227
DOI:10.1109/MIXDES.2006.1706540