Balancing Energy vs. Performance in Processors with DiscreteVoltage/Frequency Modes

• Published in: 12th IEEE International Conference on Embedded and Real-Time Computing Systems and Applications (RTCSA'06) pp. 294 - 304
• Main Authors: Marinoni, M., Buttazzo, G.
• Format: Conference Proceeding
• Language: English
• Published: IEEE 2006
• Subjects: Algorithm design and analysis; Dynamic voltage scaling; Energy consumption; Energy management; Frequency; Processor scheduling; Pulse width modulation; Real time systems; Timing; Voltage control
• ISBN: 0769526764; 9780769526768
• ISSN: 2325-1271
• DOI: 10.1109/RTCSA.2006.20

Applying classical dynamic voltage scaling (DVS) techniques to real-time systems running on processors with discrete voltage/frequency modes causes a waste of computational resources. In fact, whenever the ideal speed level computed by the DVS algorithm is not available in the system, to guarantee the feasibility of the task set, the processor speed must be set to the nearest level greater than the optimal one, thus underutilizing the system. Whenever the task set allows a certain degree of flexibility in specifying timing constraints, rate adaptation techniques can be adopted to balance performance (which is a function of task rates) vs. energy consumption (which is a function of the processor speed). In this paper, we propose a new method that combines discrete DVS management with elastic scheduling to fully exploit the available computational resources. Depending on the application requirements, the algorithm can be set to improve performance or reduce energy consumption, so enhancing the flexibility of the system. A reclaiming mechanism is also used to take advantage of early completions