High VTH and Breakdown Enhancement-Mode GaN HEMTs for Power ICs Application Using Charge Trapping Layer

This work demonstrates a high V TH (+8.4 V) and breakdown voltage (1100 V) Enhancement-mode GaN HEMTs using an \text{Al:HfO}_{\mathrm{x}} -based charge trapping layer (CTL). The operation mechanism is investigated through TCAD simulation, and the device performance is systematically evaluated throug...

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Published in2024 36th International Symposium on Power Semiconductor Devices and ICs (ISPSD) pp. 378 - 381
Main Authors Jiang, Yang, Du, Fangzhou, Wen, Kangyao, He, Jiaqi, Li, Mujun, Tang, Chuying, Zhang, Yi, Wang, Zhongrui, Wang, Qing, Yu, Hongyu
Format Conference Proceeding
LanguageEnglish
Published IEEE 02.06.2024
Subjects
Charge trapping layer (CTL)
Electric breakdown
HEMTs
High E-mode GaN HEMTs
Inverters
Logic gates
Modulation
Monolithic integrated circuits
Monolithic Integration
Noise
Performance evaluation
Power
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Summary:This work demonstrates a high V TH (+8.4 V) and breakdown voltage (1100 V) Enhancement-mode GaN HEMTs using an \text{Al:HfO}_{\mathrm{x}} -based charge trapping layer (CTL). The operation mechanism is investigated through TCAD simulation, and the device performance is systematically evaluated through static and dynamic electrical measurements. Thanks to the V TH is tunable by initialization voltage, we prove that the fabricated CTL-based GaN inverters can operate under a variety of conditions ( \beta=10-40 and \mathrm{V}_{\text{DD}}=3 V-15 V) with commendable output swing and noise margins. These results present a promising approach towards to realizing the monolithic integration of GaN devices for power ICs applications.
ISSN:1946-0201
DOI:10.1109/ISPSD59661.2024.10579575