100% operational efficient bit-serial programmable FIR digital filters

• Published in: 13th European Signal Processing Conference (EUSIPCO 2005) pp. 1 - 4
• Main Authors: Kalivas, P., Tsirikos, A., Bougas, P., Pekmestzi, K. Z.
• Format: Conference Proceeding Journal Article
• Language: English
• Published: IEEE 01.09.2005
• Subjects: Complement; Complexity; Complexity theory; Delays; Digital filters; Finite impulse response filters; Hardware; Multipliers; Registers; Shift registers; Signal processing
• ISBN: 1604238216; 9781604238211

A new scheme for the implementation of programmable FIR digital filters with 100% operational efficiency is presented in this paper. The term 100% operational efficiency implies that no zero bits have to be inserted between successive input data words in order the filter input to be synchronized with the filter output. Both the input data and the filter output are in two's complement LSB-first bit-serial form. The coefficients are in two's complement bit-parallel form. All the intermediate results and the filter output are produced and handled in full precision. The proposed scheme is based on a special serial-parallel multiplier that operates with 100% efficiency. We exploit the internal registers and the free accumulation input in this multiplier to reduce the hardware complexity of the filter significantly. The proposed scheme is compared from the aspect of hardware complexity and efficiency with other bit-serial schemes.