Path based approach for crosstalk delay analysis

• Published in: 17th International Conference on VLSI Design. Proceedings pp. 727 - 730
• Main Authors: Arvind, N.V., Rajagopal, K.A., Ajith, H.S., Das, S.
• Format: Conference Proceeding
• Language: English
• Published: Los Alamitos CA IEEE 2004; IEEE Computer Society
• Subjects: Applied sciences; Clocks; Convergence; Crosstalk; Delay effects; Design. Technologies. Operation analysis. Testing; Electronics; Exact sciences and technology; Instruments; Integrated circuits; Iterative methods; Runtime; Semiconductor electronics. Microelectronics. Optoelectronics. Solid state devices; Silicon; Timing; Very large scale integration; Integrated circuit design; Delay time; VLSI circuit; Failures; Crosstalk
• ISBN: 0769520723; 9780769520728
• DOI: 10.1109/ICVD.2004.1261013

Crosstalk delay analysis and closure is becoming crucial for first pass silicon success in current technologies. The inherent pessimism in crosstalk delay analysis results in huge number of violations to be flagged, which is both difficult to fix and to identify the real violations that could actually cause silicon failures. In this paper, we present a new approach of path based crosstalk delay analysis to reduce the inherent pessimism. The solution uses a two pass analysis approach-in the first pass all crosstalk delay violating paths are identified and in the second pass all these violations are reanalyzed more accurately to verify whether it is a real violation. The solution fundamentally relies on the fact that a path based crosstalk delay analysis is more accurate and less pessimistic, compared to net based analysis and violation identification. We also present results from various 130 nm designs showing as much as 70% reduction in violations.