Accuracy of yield impact calculation based on kill ratio

We evaluated the accuracy of yield impact calculations based on kill ratio analysis. The accuracy was calculated using computer simulated defect maps and bin maps. The results show that the yield impact was inaccurate when parametric faults caused low yield or a large number of non-killer defects we...

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Bibliographic Details
Published in13th Annual IEEE/SEMI Advanced Semiconductor Manufacturing Conference. Advancing the Science and Technology of Semiconductor Manufacturing. ASMC 2002 (Cat. No.02CH37259) pp. 87 - 91
Main Authors Ono, M., Iwata, H., Watanabe, K.
Format Conference Proceeding
LanguageEnglish
Published Piscataway NJ IEEE 2002
Subjects
Accuracy
Applied sciences
Circuit faults
Circuit testing
Computational modeling
Computer simulation
Electronics
Equations
Exact sciences and technology
General (including economical and industrial fields)
Inspection
Integrated circuit yield
Production engineering
Semiconductor device manufacture
Production line
Manufacturing defect
Electronics industry
Defect detection
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Summary:We evaluated the accuracy of yield impact calculations based on kill ratio analysis. The accuracy was calculated using computer simulated defect maps and bin maps. The results show that the yield impact was inaccurate when parametric faults caused low yield or a large number of non-killer defects were included in inspection reports. It is therefore recommended to evaluate bin maps and reduce the non-killer defects before calculating the yield impact.
ISBN:9780780371583
0780371585
ISSN:1078-8743
2376-6697
DOI:10.1109/ASMC.2002.1001580