Hardware Implementation of the Multiplier Using Argument Bit Grouping

The paper considers an approach to the construction of multipliers based on the combination of Vedic principles of multiplication and classical algorithm with summation of partial products using matrix architecture. The paper shows the algorithm realized by the multiplier, presents a variant of impl...

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Bibliographic Details
Published in2024 XXVII International Conference on Soft Computing and Measurements (SCM) pp. 238 - 241
Main Authors Bureneva, Olga I., Pavlov, Alexander P.
Format Conference Proceeding
LanguageEnglish
Published IEEE 22.05.2024
Subjects
Accelerometers
Companies
Computer architecture
Costs
Cyclones
fast multipliers
Field programmable gate arrays
FPGA based acceleration of arithmetic operations
FPGA multipliers
Hardware
hardware acceleration
matrix multiplier
multiplication by a group of digits
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Summary:The paper considers an approach to the construction of multipliers based on the combination of Vedic principles of multiplication and classical algorithm with summation of partial products using matrix architecture. The paper shows the algorithm realized by the multiplier, presents a variant of implementation of the multiplier with two-bit groupings of argument bits, estimates hardware costs and time characteristics of the obtained combinational and pipeline multipliers based on FPGA of Cyclone III family of IntelFPGA company.
DOI:10.1109/SCM62608.2024.10554181