A 1024-Channel 268 nW/pixel 36x36 μm2/ch Data-Compressive Neural Recording IC for High-Bandwidth Brain-Computer Interfaces

This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC feat...

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Bibliographic Details
Published in2023 IEEE Symposium on VLSI Technology and Circuits (VLSI Technology and Circuits) pp. 1 - 2
Main Authors Jang, MoonHyung, Yu, Wei-Han, Lee, Changuk, Hays, Maddy, Wang, Pingyu, Vitale, Nick, Tandon, Pulkit, Yan, Pumiao, Mak, Pui-In, Chae, Youngcheol, Chichilnisky, E.J., Murmann, Boris, Muratore, Dante G.
Format Conference Proceeding
LanguageEnglish
Published JSAP 11.06.2023
Subjects
Bandwidth
brain
Brain-computer interfaces
compression
interface
neural
Recording
Very large scale integration
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Summary:This paper presents a neural recording IC featuring lossy compression during digitization, thus preventing data deluge and enabling a compact active digital pixel design. The wired-OR-based compression discards unwanted baseline samples while allowing the reconstruction of spike samples. The IC features a 32x32 MEA with 36 \mu m pixel pitch and consumes 268nW per pixel from a single 1V supply. It achieves 9.8 \mu V_{RMS} input-referred noise and 0.3-5kHz bandwidth, resulting in NEF/PEF of 3.7/14.1.
ISSN:2158-9682
DOI:10.23919/VLSITechnologyandCir57934.2023.10185288