Optimized Vedic Multiplier \mathrm^\mathrm using Adder Approximations and Modified Carry Look Ahead Adders

This paper introduces an innovative approach to enhancing Vedic multipliers using approximate full adders with 2X1 multipliexers. The study compares this novel design with traditional multipliers, highlighting its superior performance in terms of area utilization, processing speed, and power efficie...

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Bibliographic Details
Published in2024 International Conference on Science Technology Engineering and Management (ICSTEM) pp. 1 - 5
Main Authors V, Gayatri, T, Amirtha, Padmapriya, S.
Format Conference Proceeding
LanguageEnglish
Published IEEE 26.04.2024
Subjects
4-bit modified carry look-ahead adders
Adders
approximate full adders using 2X1 multiplexer
Arithmetic
Digital circuits
Energy efficiency
Multiplexing
Optimized Vedic multiplier
Power demand
Scalability
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Summary:This paper introduces an innovative approach to enhancing Vedic multipliers using approximate full adders with 2X1 multipliexers. The study compares this novel design with traditional multipliers, highlighting its superior performance in terms of area utilization, processing speed, and power efficiency. Furthermore, the research extends the application of this design by implementing it with 4-bit approximate carry look-ahead adders, showcasing its adaptability and scalability across different bit widths. The experimental findings demonstrate the significant advantages of the proposed approach over conventional designs, establishing it as a promising solution for achieving efficient arithmetic operations in digital circuits.
DOI:10.1109/ICSTEM61137.2024.10561072