Bayesian Optimization of Large Glass Package Architecture for System-Level Reliability in High-Performance Computing Applications

• Published in: 2024 IEEE 74th Electronic Components and Technology Conference (ECTC) pp. 246 - 253
• Main Authors: Surillo, Emanuel Torres, Sosa, Ramon A., Molina, Christian, Park, Hyunggyu, Nimbalkar, Pratik, Srirangan, Sriram, Dahal, Lila D., Lee, Yongwon, Smet, Vanessa
• Format: Conference Proceeding
• Language: English
• Published: IEEE 28.05.2024
• Subjects: Bayes methods; Bayesian optimization; Computer architecture; Finite element analysis; Glass; Integrated circuit interconnections; Large glass BGA package; Materials reliability; Reliability engineering; system-level reliability; warpage mitigation
• ISSN: 2377-5726
• DOI: 10.1109/ECTC51529.2024.00047

In the current era of heterogeneous integration (HI), which combines chiplet-based system architectures and advanced packaging, glass has emerged as a compelling candidate for the next generation of substrate core material in high- performance electronic systems. Owing to its superior dimensional stability and subsequent warpage resistance, glass holds the potential to extend package sizes far beyond the limits of current organic substrates, aligning with predictions from HI roadmaps envisioning package sizes exceeding 100x100 mm2 in the coming years. Moreover, glass can support high-density interconnects to meet the growing die-to-die bandwidth requirements, effectively eliminating the need for silicon interposers or bridges. However, it is the uniquely customizable coefficient of thermal expansion (CTE) in a wide range between 3-10 ppm/°C that grants unparalleled design flexibility to address system-level reliability challenges in a two-level System-in-Package (SiP) hierarchy wherein chiplets are assembled on glass at very fine pitch while the glass package is directly surface mounted on the printed circuit board without the need for an intermediate organic package. To that end, understanding the conflicting demands on glass CTE is critical to achieve chip-level reliability with fine-pitch Cu pillar interconnections, control warpage induced by the chip-level assembly, subsequent yield loss in board-level reflow, and ensure board-level reliability of the ball grid array (BGA) interconnections. To address this grand challenge, this paper investigates the system-level reliability of large glass BGA packages, 100 x 100 mm2 in size, as a function of glass CTE and other materials selection and geometrical considerations. To explore this high-dimensionality parameter space, a finite element modeling framework was built and coupled to a Bayesian optimization framework to guide the design of reliable glass-based solutions with extended package sizes. Insights from the optimization results were used to guide the design and demonstration of a first prototype, presented in this paper, showcasing the potential of glass substrates to meet the ever-growing requirements of future HPC systems.